The present invention relates to a semiconductor device and, in particular, concerns a semiconductor device formed by stacking a plurality semiconductor chips, such as Dynamic Random Access Memories (DRAMs) or the like.
A semiconductor device of a Multi-Chip Package (MCP) configuration in which a semiconductor chip on an upper stage is stacked in a manner so as to overhang from a semiconductor chip on a lower stage has been known.
As a related technique, JP-A No. 2000-299431 has disclosed a technique in which an adhesive agent is placed on a wiring substrate and by flip-chip mounting a first semiconductor chip thereon, the adhesive agent is allowed to protrude the outside of the first semiconductor chip so that a protruded portion (overhang portion) of a second semiconductor chip is supported by the protruded adhesive agent.
Moreover, JP-A No. 2009-099697, JP-A No. 2009-194189 and JP-A No. 2011-086943 have disclosed a technique in which the overhang portion of the semiconductor chip on the upper stage is supported by bumps and wires.
Furthermore, JP-A No. 2013-115190 and JP-A No. 2014-082302 have disclosed a technique in which between the overhang portion of the semiconductor chip on the upper stage and the wiring substrate, an under fill or an NCP (Non-Conductive Paste) is placed.
It is supposed that the entire contents of the above-mentioned Patent Documents are incorporated and described in the present specification as quoted descriptions. The following analyses are carried out by the present inventors.
In recent years, together with miniaturization and thinness of portable apparatuses, miniaturization and thinness of a semiconductor device of the MCP configuration to be incorporated in the portable apparatuses have been achieved. For this reason, to make the chip thickness of the semiconductor chip thinner has been examined; however, the MCP in which the semiconductor chip on the upper stage is stacked so as to overhang from the semiconductor chip on the lower stage has caused the following problems.
(1) Since the thickness of the semiconductor chip on the lower stage becomes thinner, the gap between the overhang portion of the semiconductor chip on the upper stage and the wiring substrate also becomes narrower to deteriorate the filling property of a sealing resin. As a result, voids tend to be generated.
(2) Since the thickness of the semiconductor chip on the upper stage becomes thinner, the wire bonding property of the overhang portion of the semiconductor chip on the upper stage onto the electrode pads deteriorates. In other words, unjoined wires and chip cracking might occur. In the case when the amount of overhand is large, the risk of the overhang portion being pressed downward onto the substrate side by a pressure at the time of a molding process becomes higher. Moreover, since the overhang portion is lowered, the gap between the overhang portion and the wiring substrate is further narrowed. Furthermore, since the chip is lowered, the risk of chip cracking becomes higher. Since the chip is lowered, the wires are deflected, with the result that the risk of short-circuit with the adjacent wire becomes higher.
Additionally, in accordance with the technique described in JP-A No. 2000-299431, in a configuration where the semiconductor chip on the lower stage is mounted on the wiring substrate with its face up, when an attempt is made to form a supporting portion by the protruded adhesive agent, the protruded adhesive agent tends to run up onto the semiconductor chip on the lower stage, and might cover the electrodes of the semiconductor chip on the lower stage. When the chip thickness of the semiconductor chip on the lower stage is made thinner, the protruded adhesive agent more easily runs up onto the surface of the semiconductor chip on the lower stage. By the adhesive agent thus ran up thereon, the flatness of the semiconductor chip surface deteriorates, making it difficult to maintain good adhesiveness onto the semiconductor chip on the upper stage.
Moreover, in accordance with the technique in which the overhang portion of the semiconductor chip on the upper stage is supported by bumps and wires, disclosed by JP-A No. 2009-099697, JP-A No. 2009-194189 and JP-A No. 2011-086943, in the case when the semiconductor chip on the upper stage is thin, with the amount of overhang being large, a problem is raised in that a gap between the semiconductor chip on the upper stage and the supporting portion of the semiconductor chip on the lower stage tends to form a concave portion by a pressure at the time of molding. Consequently, the concave portion of the overhang portion might deteriorate the filling property of the sealing resin, or might generate chip cracking.
Furthermore, in accordance with the technique in which between the overhang portion of the semiconductor chip on the upper stage and the wiring substrate, an under fill or a Non-Conductive Paste (NCP) is placed, disclosed by JP-A No. 2013-115190 and JP-A No. 2014-082302, in the case when the semiconductor chip on the upper stage is thin, with the amount of overhang being large, before the under fill or the NCP has been filled and cured under the overhang portion, the overhang portion might be deflected to deteriorate the flatness. It is difficult to control the application area by the under fill or the NCP, and since it becomes further difficult when the semiconductor chip on the lower stage is thin, the application is basically made over the entire region of the overhang portion. Therefore, the running up onto the side faces of the semiconductor chip on the upper stage tends to occur, and in the case when the semiconductor chip on the upper stage is thin, the electrodes of the semiconductor chip on the upper stage might be covered with the under fill or the NCP that ran up thereon.